Under the "Misc" tab, there is an item called the Force Gate. It's tooltip says "ForceGate Selected." which doesn't help. I am confused as to how to use the Force Gate, and it doesn't seem to be documented anywhere either. Please help!
I have a simple circuit using some latches and tri-state drivers.
On one clock, I get a stack overflow message but it is not obvious why.
The fault occurs when the WR input is manually toggled from 0 to 1.
The Verilog text is here:
* This is an autogenerated netlist code from CircuitVerse. Verilog Code can be
* tested on https://www.edaplayground.com/ using Icarus Verilog 0.9.7. Thi...
The link https://circuitverse.org/testbench appears to be broken (I get a 404 error). Where can I find the test data generator, or at least a description of how to build a JSON file to load into a TB_Input?