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Having the tool generate a complete truth table for a schematic I have entered

Created by JM• 9 months ago

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Comparing 32-bit values with bitwise XOR is resulting in undefined bits. https://circuitverse.org/users/120210/projects/xor-gate-tests

Created by Bruno Krugel• 10 months ago

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Under the "Misc" tab, there is an item called the Force Gate. It's tooltip says "ForceGate Selected." which doesn't help. I am confused as to how to use the Force Gate, and it doesn't seem to be documented anywhere either. Please help!

Created by Antrotherkus• 1 year ago

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Please help with this issue

Created by Andrew• 11 months ago

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Is it possible to get the Clock faster than 50ms? i found a way to double its speed up to 25ms but thats still too slow for my needs. Thanks for reading

Created by Belinus• 12 months ago

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How do i generate a truth table?

Created by O.Webster• 12 months ago

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I am not able to join the elements in the circuit what am I supposed to do now?

Created by Rajesh R• 12 months ago

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Why I am not able to connect the wires

Created by Rajesh R• 12 months ago

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I have a simple circuit using some latches and tri-state drivers. On one clock, I get a stack overflow message but it is not obvious why. The fault occurs when the WR input is manually toggled from 0 to 1. The Verilog text is here: /** * This is an autogenerated netlist code from CircuitVerse. Verilog Code can be * tested on https://www.edaplayground.com/ using Icarus Verilog 0.9.7. Thi...

Created by Kurt Zierhut• 12 months ago

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The link https://circuitverse.org/testbench appears to be broken (I get a 404 error). Where can I find the test data generator, or at least a description of how to build a JSON file to load into a TB_Input?

Created by stu• 2 years ago

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