How to use the include command in verilog to use another sub-circuit in the same project?
General • Asked about 2 months ago by Cesar Andrey Perdomo
Cesar Andrey Perdomo
Commented on
Nov 30, 2020:
Example:
Subcircuit verilog Halfadder
module HalfAdder (a,b,s,c);
input a,b;
output s,c;
wire nand_2_out_0,nand_3_out_0,nand_0_out_0,not_0_out_0,nand_1_out_0;
nand nand_2 (nand_2_out_0,nand_0_out_0,b);
nand nand_3 (nand_3_out_0,nand_1_out_0,nand_2_out_0);
assign s = nand_3_out_0;
nand nand_0 (nand_0_out_0,a,b);
not not_0 (not_0_out_0,nand_0_out_0);
assign c = not_0_out_0;
nand nand_1 (nand_1_out_0,a,nand_0_out_0);
endmodule
Sub-circuit verilog Fulladder
include HalfAdder ???
module FullAdder (a,b,cin,s,cout);
input a,b,cin;
output s,cout;
wire HalfAdder_0_out_0,HalfAdder_0_out_1,HalfAdder_1_out_0,HalfAdder_1_out_1,or_0_out_0;
HalfAdder HalfAdder_0 (a,b,HalfAdder_0_out_0,HalfAdder_0_out_1);
HalfAdder HalfAdder_1 (HalfAdder_0_out_0,cin,HalfAdder_1_out_0,HalfAdder_1_out_1);
or or_0 (or_0_out_0,HalfAdder_1_out_1,HalfAdder_0_out_1);
assign cout = or_0_out_0;
assign s = HalfAdder_1_out_0;
endmodule
Satvik Ramaprasad
Commented on
Dec 03, 2020:
Cesar, simply include both modules in one file. It figures out which is the root module automatically.
For example, this will work:
// Half adder
module halfadder(
input a,
input b,
output o,
output c
);
assign o = a ^ b;
assign c = a & b;
endmodule
// Full adder
module fulladder(
input a,
input b,
input d,
output o,
output c
);
logic t, c1, c2;
halfadder ha1(a, b, t, c1);
halfadder ha2(t, d, o, c2);
assign c = c1 | c2;
endmodule
