Community

Example:

Subcircuit verilog Halfadder

module HalfAdder (a,b,s,c); input a,b; output s,c; wire nand2out0,nand3out0,nand0out0,not0out0,nand1out0; nand nand2 (nand2out0,nand0out0,b); nand nand3 (nand3out0,nand1out0,nand2out0); assign s = nand3out0; nand nand0 (nand0out0,a,b); not not0 (not0out0,nand0out0); assign c = not0out0; nand nand1 (nand1out0,a,nand0out0); endmodule

Sub-circuit verilog Fulladder

include HalfAdder ???

module FullAdder (a,b,cin,s,cout); input a,b,cin; output s,cout; wire HalfAdder0out0,HalfAdder0out1,HalfAdder1out0,HalfAdder1out1,or0out0; HalfAdder HalfAdder0 (a,b,HalfAdder0out0,HalfAdder0out1); HalfAdder HalfAdder1 (HalfAdder0out0,cin,HalfAdder1out0,HalfAdder1out1); or or0 (or0out0,HalfAdder1out1,HalfAdder0out1); assign cout = or0out0; assign s = HalfAdder1out0; endmodule

Cesar, simply include both modules in one file. It figures out which is the root module automatically.

For example, this will work:

// Half adder module halfadder( input a, input b, output o, output c );

assign o = a ^ b; assign c = a & b;

endmodule

// Full adder module fulladder( input a, input b, input d, output o, output c );

logic t, c1, c2;

halfadder ha1(a, b, t, c1); halfadder ha2(t, d, o, c2);

assign c = c1 | c2;

endmodule