Searched Projects

Tags: GATES

project.name
0 Stars     21 Views

REALIZATION OF ALL GATES USING NAND GATE

REALIZATION OF ALL GATES USING NAND GATE

project.name
0 Stars     23 Views

RAJAT GATE

RAJAT GATE

project.name
0 Stars     21 Views
User:

GATES

GATES

project.name
0 Stars     18 Views

EXP 1a

EXP 1a

project.name
0 Stars     34 Views
User:

24/08/21

24/08/21

project.name
0 Stars     20 Views

not gate

not gate

The output is the opposite of its input


project.name
0 Stars     17 Views

or gate

or gate

The output can be 1 if at least of the inputs is 1 otherwise the output is 0


project.name
0 Stars     25 Views

and gate

and gate

The output will be 1 if only the two input is 1.


project.name
0 Stars     23 Views

xor gate

xor gate

The output is 1 if only if one input is 1 otherwise the output is 0


project.name
0 Stars     21 Views

using nor gate

using nor gate

CREATION OF NOT ,OR, AND GATE USING NOR GATE


project.name
0 Stars     23 Views
User:

ALIYAS BABU

ALIYAS BABU

project.name
0 Stars     15 Views

LAB 1

LAB 1

project.name
0 Stars     424 Views

FULL ADDERS

FULL ADDERS

Full Adder is the adder that adds three inputs and produces two outputs. The first two inputs are A and B and the third input is an input carry as C-IN. The output carry is designated as C-OUT and the normal output is designated as S which is SUM. A full adder logic is designed in such a manner that can take eight inputs together to create a byte-wide adder and cascade the carry bit from one adder to another. we use a full adder because when a carry-in bit is available, another 1-bit adder must be used since a 1-bit half-adder does not take a carry-in bit. A 1-bit full adder adds three operands and generates 2-bit results.

Here we need to make a full adder on simulator by using gate ie.  XOR gate and NAND gate  after that we need to check whether it is right or not by giving input 0 or 1 . As we have already make a truth table for it in order to check and match whether the circuit is connected or working properly well or not. 


TRUTH TABLE





project.name
1 Stars     237 Views

A decoder is a multiple input, multiple output logic circuit that changes codes i/ps into coded o/ps, where both the inputs and outputs are dissimilar for instance n-to-2n, and binary coded decimal decoders. Decoding is essential in applications like data multiplexing, memory address decoding, and 7 segment display. The best example of decoder circuit would be an AND-gate because when all its inputs are “High.”, the output of this gate is “High” which is called “active High output”. As an alternative to AND gate, the NAND gate is connected the output will be “Low” (0) only when all its inputs are “High”. Such o/p is called “active low output”.

2 to 4 Line Decoder 

In this type of decoders, decoders have two inputs namely A0, A1, and four outputs denoted by D0, D1, D2, and D3. As you can see in the following truth table – for every input combination, one o/p line is turned on.D0 =A1 A0, ( minterm m0) which corresponds to input 00 D1 =A1 A0, ( minterm m1) which corresponds to input 01 D2 =A1 A0, ( minterm m2) which corresponds to input 10 D3 =A1 A0, ( minterm m3) which corresponds to input 11.

The circuit is implemented using AND gates. In this circuit, the logic equation for D0 is A1/A0, and so on. Thus, each output of the decoder will be generated to the input combination.

Truth Table



project.name
0 Stars     198 Views

Multiplexer is a combinational circuit that has maximum of 2n data inputs, ‘n’ selection lines and single output line. One of these data inputs will be connected to the output based on the values of selection lines.

Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros and ones. So, each combination will select only one data input. Multiplexer is also called as Mux.

4x1 Multiplexer

4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one output Y. The block diagram of 4x1 Multiplexer is shown in the following figure.



One of these 4 inputs will be connected to the output based on the combination of inputs present at these two selection lines. Truth table of 4x1 Multiplexer is shown below.

TRUTH TABLE


Selection LinesOutputS1S0Y00I001I110I211I3


From Truth table, we can directly write the Boolean function for output, Y as

Y=S1S0I0+S1S0I1+S1S0I2+S1S0I3Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I3

We can implement this Boolean function using Inverters, AND gates & OR gate. The circuit diagram of 4x1 multiplexer is shown in the following figure.

CIRCUIT DAIGRAM

                                     


project.name
0 Stars     241 Views

Binary to Gray code conversion

The Binary to Gray code converter is a logical circuit that is used to convert the binary code into its equivalent Gray code. By putting the MSB of 1 below the axis and the MSB of 1 above the axis and reflecting the (n-1) bit code about an axis after 2n-1 rows, we can obtain the n-bit gray code.

In 4-bit gray code, the 3-bit code is reflected against the axis drawn after the 24-1-1th =8th row.

                                        

Just like Binary to Gray code conversion; it is also a very simple process. There are the following steps used to convert the Gray code into binary.

  • Just like binary to gray, in gray to binary, the 1st bit of the binary number is similar to the MSB of the Gray code.
  • The 2nd bit of the binary number is the same as the 1st bit of the binary number when the 2nd bit of the Gray code is 0; otherwise, the 2nd bit is altered bit of the 1st bit of binary number. It means if the 1st bit of the binary is 1, then the 2nd bit is 0, and if it is 0, then the 2nd bit be 1.
  • The 2nd step continues for all the bits of the binary number.

                                         


project.name
0 Stars     87 Views

8x1 Multiplexer

In the 8 to 1 multiplexer, there are total eight inputs, i.e., A0, A1, A2, A3, A4, A5, A6, and A7, 3 selection lines, i.e., S0, S1and S2 and single output, i.e., Y. On the basis of the combination of inputs that are present at the selection lines S0, S1, and S2, one of these 8 inputs are connected to the output.

Let the 8x1 Multiplexer has eight data inputs I7 to I0, three selection lines s2, s1 & s0 and one output Y. The Truth table of 8x1 Multiplexer is shown below.




 BLOCK DIAGRAM




project.name
0 Stars     14 Views
User:

Untitled

Untitled

project.name
0 Stars     37 Views

project.name
0 Stars     21 Views
User:

GATES

GATES

project.name
0 Stars     16 Views
User:

GATES

GATES

project.name
0 Stars     17 Views
User:

GATES

GATES

project.name
0 Stars     19 Views
User:

GATES

GATES

project.name
0 Stars     18 Views
User:

GATES

GATES

project.name
0 Stars     19 Views
User:

ECE

ECE

project.name
0 Stars     19 Views
User:

EXPERIMENT 5

EXPERIMENT 5

project.name
0 Stars     10 Views

EX 1 level 1 and 2

EX 1 level 1 and 2

project.name
0 Stars     7 Views

Sneha Hanamaraddi

Sneha Hanamaraddi

project.name
0 Stars     8 Views
User:

AND_OR_NOT_GATE

AND_OR_NOT_GATE

project.name
0 Stars     11 Views
User:

NAND_AS_AND_OR_NOT

NAND_AS_AND_OR_NOT

project.name
0 Stars     8 Views
User:

XNOR_XOR

XNOR_XOR

project.name
0 Stars     8 Views
User:

NAND_OR

NAND_OR

project.name
0 Stars     7 Views
User:

NAND_AS_EXNOR_EXNOR

NAND_AS_EXNOR_EXNOR

project.name
0 Stars     10 Views
User:

NOR_AS_EXNOR_EXOR

NOR_AS_EXNOR_EXOR

project.name
0 Stars     8 Views
User:

Untitled

Untitled

project.name
0 Stars     8 Views
User:

dd main

dd main

project.name
0 Stars     9 Views
User:

Experiment 1

Experiment 1

project.name
0 Stars     4 Views

HANEEFA NADEEM AHMAD

HANEEFA NADEEM AHMAD

project.name
0 Stars     4 Views

ANKITHA SARIKA PRAMOD

ANKITHA SARIKA PRAMOD

project.name
0 Stars     4 Views

SPARSHA

SPARSHA

project.name
0 Stars     7 Views

Untitled

Untitled

project.name
0 Stars     6 Views
User:

GATE

GATE

project.name
0 Stars     4 Views
User:

PRAJWAL S

PRAJWAL S

project.name
0 Stars     7 Views
User:

PRAJWAL S

PRAJWAL S

project.name
0 Stars     5 Views
User:

VISHAL H

VISHAL H

project.name
0 Stars     5 Views
User:

PRAJWAL S

PRAJWAL S

project.name
0 Stars     6 Views
User:

PRAJWAL S

PRAJWAL S

project.name
0 Stars     5 Views
User:

PRAJWAL S

PRAJWAL S

project.name
0 Stars     9 Views
User:

Basic Gates

Basic Gates

Basic Gates


project.name
0 Stars     6 Views
User:

basic gates

basic gates

project.name
0 Stars     5 Views
User:

basic gate

basic gate

basic gate


project.name
0 Stars     4 Views
User:

Navya.C

Navya.C

project.name
0 Stars     6 Views
User:

Navya.C

Navya.C

project.name
0 Stars     4 Views
User:

VINAY R

VINAY R

GATE


project.name
0 Stars     8 Views

HARSHITH GOWDA S

HARSHITH GOWDA S

GATES


project.name
0 Stars     10 Views
User:

NARENDRA

NARENDRA

project.name
0 Stars     8 Views
User:

NARENDRA

NARENDRA

project.name
0 Stars     9 Views
User:

NARENDRA

NARENDRA

project.name
0 Stars     7 Views

MD SAAD

MD SAAD

project.name
0 Stars     4 Views

NITHYA

NITHYA

project.name
0 Stars     7 Views

LAWS

LAWS

project.name
0 Stars     8 Views
User:

EXPERIMENT 2 LEVEL 1

EXPERIMENT 2 LEVEL 1

project.name
0 Stars     10 Views

Untitled

Untitled

project.name
0 Stars     6 Views
User:

GATES

GATES

project.name
0 Stars     5 Views

MUX 2:1 USING GATES

MUX 2:1 USING GATES

Here we have used 1 NOT gate, 2 AND gates & 1 OR gate.


project.name
0 Stars     5 Views

MUX 4:1 using Gates

MUX 4:1 using Gates

project.name
0 Stars     5 Views
User:

EXP 3

EXP 3

project.name
0 Stars     5 Views
User:

MUX 2:1

MUX 2:1

project.name
0 Stars     6 Views
User:

DE -MUX

DE -MUX

project.name
0 Stars     5 Views

20221C0M0043 R.LOKESH SAI NAIK

20221C0M0043 R.LOKESH SAI NAIK

project.name
0 Stars     4 Views
User:

Untitled

Untitled

project.name
0 Stars     4 Views
User:

LOGIC GATES

LOGIC GATES

project.name
0 Stars     4 Views

PKT CIRCUIT

PKT CIRCUIT

project.name
0 Stars     4 Views
User:

VERIFICATION OF LOGIC GATES

VERIFICATION OF LOGIC GATES

TO KNOW THE GATES


project.name
0 Stars     3 Views
User:

verification of logic gates 1

verification of logic gates 1

project.name
0 Stars     3 Views

CIRCUIT VIRSE

CIRCUIT VIRSE

CIRCUIT VIRSE


project.name
0 Stars     2 Views
User:

DEEPU2

DEEPU2

project.name
0 Stars     3 Views
User:

DEEPU3

DEEPU3

project.name
0 Stars     2 Views
User:

DEEPU4

DEEPU4

project.name
0 Stars     4 Views
User:

EXPM 2 LEEPI9KA 20241CAI0115

EXPM 2 LEEPI9KA 20241CAI0115

project.name
0 Stars     3 Views
User:

LOGIC GATES 2

LOGIC GATES 2

project.name
0 Stars     3 Views

Himanshu Tyagi

Himanshu Tyagi

project.name
0 Stars     3 Views

LOGIC GATES

LOGIC GATES

AND GATE , OR GATE,  NOT GATE ,NAND GATE, NOR GATE; XOR AND XNOR GATE


project.name
0 Stars     3 Views
User:

MEGHANA P

MEGHANA P

project.name
0 Stars     3 Views
User:

Exp 0161

Exp 0161

project.name
0 Stars     2 Views
User:

Untitled

Untitled

project.name
0 Stars     2 Views
User:

Basic logic gates

Basic logic gates