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Balgovind Rana

Member since: 3 months

Educational Institution: Presidency University, Bangalore

Country: India

First DG

First DG
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MONTHDGATE

MONTHDGATE
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Experiment 1

Experiment 1
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EXPERIMENT NO.2

EXPERIMENT NO.2
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EXPERIMENT NO. 3 ( LEVEL 2)

EXPERIMENT NO. 3 ( LEVEL 2)
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Verification of logic gates

Verification of logic gates
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Untitled

Untitled
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Verification of logic gates

Verification of logic gates
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Verification of logic gates

Verification of logic gates
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Verification of logic gates

Verification of logic gates
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Experimet No. 4

Experimet No. 4
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Untitled

Untitled
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Untitled

Untitled
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implemetation

implemetation
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Design of Half ADDER Circuit

Design of Half ADDER Circuit
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implemetation gates

implemetation gates
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Untitled

Untitled
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EXPERIMENT NO. 05 ( COMPARATOR)

EXPERIMENT NO. 05 ( COMPARATOR)
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2-Bit Comparator using NAND gate

2-Bit Comparator using NAND gate
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EX N0 : 05 (1-BIT MAGNITUDE COMPARATOR BASIC GATES)

EX N0 : 05 (1-BIT MAGNITUDE COMPARATOR BASIC GATES)
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1 bit basic gates

1 bit basic gates
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EX NO 05 ( 2-BIT USING NAND GATE)

EX NO 05 ( 2-BIT USING NAND GATE)
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Experiment No : 06

Experiment No : 06
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