This project showcases a Trit RAM designed for ternary logic simulation within CircuitVerse. The RAM features 729 addresses, arranged in 27 columns and 27 rows, all controlled by 3 trits for both row and column selection. This design represents an efficient approach to ternary memory, pushing the limits of CircuitVerse's simulation capabilities.

While the original goal was to create a RAM with 19,683 addresses, the complexity caused significant performance issues in the simulator, prompting a scaled-down version that operates smoothly on standard hardware.

Key Details:

• Memory Size: 729 addresses (3^6).
• Addressing Scheme: 3 trits each for row and column selection, enabling precise access to memory cells.
• Splitters as Wires: Due to CircuitVerse’s limitations, splitters are treated as single wires to maintain simulation efficiency.
• Performance Optimization: Designed to balance functionality and simulator stability, making it ideal for testing ternary logic concepts like ALUs and memory structures.

This project is an essential building block for advancing ternary computing within a binary-focused simulation tool, paving the way for innovative designs.