UNTITLED
UNTITLED1) VERIFICATION OF LOGIC GATES
2)DESIGN OF HALF ADDERS, FULL ADDERS
3) DESIGN OF HALF SUBTRACTOR, FULL SUBTRACTOR
4) Y=AB'+A'B
F(A,B,C)=(A'B+C) XNOR (AC'+BC).
EXPERIMENT 2
EXPERIMENT 2
J YAMUNA
J YAMUNA
EXP 2
EXP 2
EXPERIMENT 2
EXPERIMENT 2
EXPERIMENT 2
EXPERIMENT 2
level 3
level 3
EXPERRIMENT 2
EXPERRIMENT 2AISHWARYA
EXPERIMENT 2: VERIFICATION OF BOOLEAN LAWS
EXPERIMENT 2: VERIFICATION OF BOOLEAN LAWS
Experiment - 02
Experiment - 02ZEEYA UL HAQ
20231CSE0662
Experinment - 4
Experinment - 4
Experinment - 4
Experinment - 4
EXPERIMENT 2 (LEVEL 1)
EXPERIMENT 2 (LEVEL 1)VERIFICATION OF BOOLEAN LAWS (PAGE NO. 17, 18 & 19)
