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Tags: Q2 = 0

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User Image Avinash Raj

DLD Q1

DLD Q1
Determine the state of the shift register after each clock pulse for the given RIGHT/(LEFT) ̅ control input waveform. Assume that Q0 = 1 Q1 = 1 Q2 = 0 and Q3 = 1 and that the serial data-input line is LOW.
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