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Any reliable sources for learning Verilog here? I tried to learn Verilog but everyone's code is producing error messages.

Created by Bielessin • 12 months ago
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Bielessin

On  Jul 05, 2023

I'm looking for reliable sources to learn Verilog here but I'm having a hard time. Every resource and project up to this point is screaming with an error message at me. Like these:

https://circuitverse.org/users/78149/projects/verilog-gates

https://circuitverse.org/users/83491/projects/verilog-56b1b150-da09-4d92-bc07-fca70a47fe60

https://circuitverse.org/users/147920/projects/verilog-practice-d6c60b40-a241-407c-a4a5-a8347a2481e6

https://circuitverse.org/users/82915/projects/verilog-module-add

And I tried to use basic code from circuitberse.org, but even this code for simple gates is producing contention errors:

module and_gate(input a, input b, output c); assign c = a & b; endmodule

Why is this happening? Any tips for learning and running Verilog here?

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Robin Hodson

On  Jul 07, 2023

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