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I'm looking for reliable sources to learn Verilog here but I'm having a hard time. Every resource and project up to this point is screaming with an error message at me. Like these:

https://circuitverse.org/users/78149/projects/verilog-gates

https://circuitverse.org/users/83491/projects/verilog-56b1b150-da09-4d92-bc07-fca70a47fe60

https://circuitverse.org/users/147920/projects/verilog-practice-d6c60b40-a241-407c-a4a5-a8347a2481e6

https://circuitverse.org/users/82915/projects/verilog-module-add

And I tried to use basic code from circuitberse.org, but even this code for simple gates is producing contention errors:

module and_gate(input a, input b, output c); assign c = a & b; endmodule

Why is this happening? Any tips for learning and running Verilog here?

There's a nice quick Verilog tester here: https://www.jdoodle.com/execute-verilog-online/

EDA Playground has some Verilog examples: https://www.edaplayground.com/playgrounds?searchString=&language=SystemVerilog%2FVerilog&simulator=&methodologies=&_libraries=on&_svx=on&_easierUVM=on&curated=true&_curated=on