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shift registers

shift registers

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sipo

sipo

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sipo

sipo

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sipo

sipo

{"layout":{"width":100,"height":140,"title_x":50,"title_y":13,"titleEnabled":true},"verilogMetadata":{"isVerilogCircuit":false,"isMainCircuit":false,"code":"// Write Some Verilog Code Here!","subCircuitScopeIds":[]},"allNodes":[{"x":-20,"y":10,"type":0,"bitWidth":1,"label":"Clock","connections":[]},{"x":-20,"y":-10,"type":0,"bitWidth":1,"label":"T","connections":[]},{"x":20,"y":-10,"type":1,"bitWidth":1,"label":"Q","connections":[]},{"x":20,"y":10,"type":1,"bitWidth":1,"label":"Q Inverse","connections":[]},{"x":10,"y":20,"type":0,"bitWidth":1,"label":"Asynchronous Reset","connections":[]},{"x":0,"y":20,"type":0,"bitWidth":1,"label":"Preset","connections":[]},{"x":-10,"y":20,"type":0,"bitWidth":1,"label":"Enable","connections":[]}],"id":51765860407,"name":"Main","TflipFlop":[{"x":520,"y":470,"objectType":"TflipFlop","label":"","direction":"RIGHT","labelDirection":"LEFT","propagationDelay":10,"customData":{"nodes":{"clockInp":0,"dInp":1,"qOutput":2,"qInvOutput":3,"reset":4,"preset":5,"en":6},"constructorParamaters":["RIGHT",1]}}],"restrictedCircuitElementsUsed":[],"nodes":[],"scopes":[],"logixClipBoardData":true}


project.name
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sipo

sipo

project.name
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PIPO Shift register

PIPO Shift register