2-bit register with S selection bit and by J-K Flip Flop
2-bit register with S selection bit and by J-K Flip Flop a 2-bit register, which has a selection bit S. If S is 0, the register will perform a parallel load. On the other hand, if S is 1, the register will perform an exchange operation. In exchange operation, the present output of the flip-flops will exchange their values, i.e., output 00 will become 00, output 11 will become 11, output 10 will become 01, and output 01 will become 10. this register is designed using J-K flip-flops and basic gates.
