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It's a 4 bit Serial In Parallel Out (SIPO) shift register. Here I've used 4 D f/f s. We have to give 1 input and we can get 4 parallel outputs from those 4 f/f s.

Realization:-

1. When we give the input 0 and clock is enable then at each clock pulse(positive edged) 0 is shifted to the 4 f/f s respectively besides it we can get the 4 parallel outputs (0) .
2. When the input is 1 and clock is enable then at each clock pulse(positive edged) , 1 is shifted to the 4 f/f s respectively and we can also get 4 parallel outputs (1) .

It's a 4 Bit Parallel In Serial Out (PIPO) shift register. I've used 4 D f/f s here. As it's parallel in so, 4 different inputs are given to each f/f and also 4 different Outputs are there from each f/f s. 

Realization:-

When the clock is enable at each positive edged clock pulse the we can get the outputs as the given inputs (i.e if input is 1010 the the output will be also same 1010 after 4 positive edged clock pulse).