It's a 4 bit Serial In Parallel Out (SIPO) shift register. Here I've used 4 D f/f s. We have to give 1 input and we can get 4 parallel outputs from those 4 f/f s.

Realization:-

1. When we give the input 0 and clock is enable then at each clock pulse(positive edged) 0 is shifted to the 4 f/f s respectively besides it we can get the 4 parallel outputs (0) .
2. When the input is 1 and clock is enable then at each clock pulse(positive edged) , 1 is shifted to the 4 f/f s respectively and we can also get 4 parallel outputs (1) .