CSC4536-new
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Author: Gaël Thomas

Project access type: Public

Description:

A complete 8-bit CPU starting from a nand for the students of Telecom SudParis/Institut Polytechnique de Paris. You can find the lab (in french, sorry:)) here: https://www-inf.telecom-sudparis.eu/cours/CSC4536/web/?page=TPs/logic/logic&soluce=true.

The processor consists in:

  • 8 8-bits registers
  • A ROM of 32 bytes and a RAM of 256 bytes. Addresses from 0 to 31 goes to the ROM, the others to the RAM
  • A simple instruction set inspired by MIPS (lw, sw, addiu, addu, etc...)

In details, we build the circuits one after the other, and as soon as we have implemented them, we reuse the ones provided by circuitverse. For the basic circuits, we have

  • nand and nand-cc: to explain how we use circuitverse (optional)
  • gates: to understand how we can build the gates (optional)
  • z4?: returns 0 if a 4-bit value is equal to 0 (required)
  • 1-to-8: replicates a bit 8 times in a 8-bit value (optional)
  • half-add, 1-add, 4-add: step by step implementation of a (4 bits) adder (optional)
  • 1x1-mux, 1x2-mux, 2x2-mux: step by step implementation of a (2x2bits) multiplexers (optional)
  • ADD: a simple ALU only able to execute add (required)
  • ADD/AND: an ALU able to do AND/ADD based operations (optional)
  • shr-1, shr-2, shr-4, shr, revert, barrel-shifter: step by step implementation of a Barrel-Shifter (optional)
  • ALU: an ALU able to do AND/ADD/SHR based operations (optional)
  • SR-nand, JK-flip-flop, half-D-flip-flop, D-flip-flop-initial, D-flip-dlop-driver, D-flip-flop: step by step implementation of a (one bit) D-flip-flop
  • 2x1-demux: a 1-bit demultiplexer with 4 outputs (optional)
  • 4-RAM: shows how we can implement a pseudo-RAM of 4 bytes from registers (optional)

For the CPU, we have:

  • CPU-v0: a circuit that increments a register at each clock cycle
  • REGS: a helper that simplifies the use of a register
  • CPU-V1: the beginning of the final CPU. Just use REGS with a register
  • MINI-PC: a circuit that performs an increment module 5. Used for the loop that fetches the instructions from memory. 
  • CPU-V2: connect the MINI-PC to the REGS
  • REGISTERS: a helper based on REGS that hides the complexity of managing 8 registers
  • CPU-V3: the CPU-v2 with 8 registers and the REGISTERS circuit
  • insn-builder: a helper circuit able to compute the value of an instruction from simple inputs
  • MICROCODE: the microcode used by the processor (a loop that (i) loads the first 8-bytes of the instruction in %insnl, increments PC, loads the next 8 bytes in %insnh, increments PC and executes the instruction)
  • CPU-v4: connect the MICROCODE to the CPU-V3 (to MINI-PC). At each cycle, the MICROCODE outputs the instruction that we have to execute.
  • DECODER: instruction decoder
  • CPU-v5: connect the DECODER to CPU-v4
  • CPU: the final CPU. Technically CPU-v5 with an ALU and a memory composed by a ROM (addresses 0 to 31) and a RAM (addresses from 32 to 256). 

The CPU executes the code "char x; while(true) x++;" where x is located at address 0xff. In details, the CPU executes this code, which is located in ROM:

  •   li %r0, 0xff.     /* implemented with addiu %r0, 0xff */
  • lab:
  •   lw %r1, (%r0)
  •   addiu %r1, 1
  •   sw %r1, (%r0)
  •   br lab             /* implemented with addiu %pc, -8 */

Created: Nov 30, 2020

Updated: Nov 15, 2021

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Comments

Just starting at learning cpu design as a hoppy and this is great.

I want more instructions specifically conditional branch instructions.

I was thinking to add a flags register and feed it into the decoder too.

The current structure of the instruction set does not have any free room in instrl register though to use for the conditions.

Wonder if you have any suggestions?

Posted on May 14 2021 at 06:29PM UTC.
+2

lets make an x64 bit cpu reigister and an 1gb ram or try to make better cpu than intel lol

Posted on Aug 17 2021 at 07:16AM UTC. Last modified by Alan on Aug 17 2021 at 07:16AM UTC.
+0

Hi Douglas! A late answer :) Implementing the condition function is easy: you can use the bits 6/7 of insnh, which are used to build the bits 4 and 5 of the function when mod=0. After, I tried to add a flags register (just like the x86 rflags), but I failed: connecting it is really a mess!

Posted on Nov 15 2021 at 11:32AM UTC.
+1

Reply to Alan: 64 bits can't be done on circuitverse, the max is 32 bits. but i like the idea of it!

oh and the making of a better processor than intel might be impossible. idk however.

Posted on Dec 18 2021 at 02:14AM UTC.
+1

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