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prateek sachan

Member since: 3 years

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HW 4

HW 4
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2421 TO 84-2-1

2421 TO 84-2-1
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COMMON CATHODE WITH DON'T CARES

COMMON CATHODE WITH DON'T CARES
Public
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COMMON ANODE with / without DON'T CARE

COMMON ANODE with / without DON'T CARE
Public
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CAT 2 Q2

CAT 2 Q2
Public
project.name

Q1 THEORY

Q1 THEORY
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hw 5

hw 5
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F'16:1 MUX

F'16:1 MUX
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8:1 A

8:1 A
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C

C
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B8X1

B8X1
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C1

C1
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b1

b1
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code1

code1
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CODE2

CODE2
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CODE3

CODE3
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CODE4

CODE4
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74LS194 TASK 5

74LS194 TASK 5
Public
project.name

3*8 decoder using 2*4

3*8 decoder using 2*4
Public
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3*8 DECODER USING TWO 2*4 DECODERS

3*8 DECODER USING TWO 2*4 DECODERS
Public
project.name

3 by 8 decoder using only two (2 by 4)

3 by 8 decoder using only two (2 by 4)
Public
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4:16 decoder using 3:8

4:16 decoder using 3:8
Public
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REG NO USING DECODER

REG NO USING DECODER
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HW 4

HW 4
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HW -3

HW -3
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DLCD THEORY TASK-1

DLCD THEORY TASK-1
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DLCD DA1

DLCD DA1
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DLCD DA1

DLCD DA1
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DLCD DA1

DLCD DA1
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task v homework dlcd PIPO SHIFT REGISTER USING DFF

task v homework dlcd PIPO SHIFT REGISTER USING DFF
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task 5hw nand gate circuit

task 5hw nand gate circuit
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COMMON ANODE WITHOUT DON'T CARES

COMMON ANODE WITHOUT DON'T CARES
Public
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CAT 1 Q4

CAT 1 Q4
Public
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CAT 1 Q7

CAT 1 Q7
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CAT 1 Q7

CAT 1 Q7
Public
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CAT 1 Q8

CAT 1 Q8
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CAT 1 Q8

CAT 1 Q8
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CAT 1 Q5

CAT 1 Q5
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CAT 1 Q5

CAT 1 Q5
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CAT 2 Q4

CAT 2 Q4
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CAT 2 Q5 DECODER CIRCUIT

CAT 2 Q5 DECODER CIRCUIT
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CAT 2 Q5 DECODER CIRCUIT

CAT 2 Q5 DECODER CIRCUIT
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CAT 2 Q5 - 4:16 Decoder using NOR logic.

CAT 2 Q5 - 4:16 Decoder using NOR logic.
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CAT 2 Q7

CAT 2 Q7
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project.name

CAT 2 Q7

CAT 2 Q7
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CAT 2 Q9

CAT 2 Q9
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CAT 2 Q8

CAT 2 Q8
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project.name

CAT 2 Q9

CAT 2 Q9
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14 LAB PRACTICE

14 LAB PRACTICE
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14 LAB PRACTICE

14 LAB PRACTICE
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PRATEEK LAB HW

PRATEEK LAB HW
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FAT 20MIC0130

FAT 20MIC0130
Public
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3:8 DECODER USING 2:4 DECODER

3:8 DECODER USING 2:4 DECODER
Public
project.name

3 by 8 decoder using only two (2 by 4)

3 by 8 decoder using only two (2 by 4)
Public
project.name

3:8 DECODER USING 2:4

3:8 DECODER USING 2:4
Public
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CAT 1 Q4

CAT 1 Q4
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D

D
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TASK 3 16:1MUX DESIGN

TASK 3 16:1MUX DESIGN
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A1

A1
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D

D
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Universal Shift Register

Universal Shift Register
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CAT 1 Q4

CAT 1 Q4
Public
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Q1-SEVEN SEGMENT DECODER TO DISPLAY NAME & REG NO

Q1-SEVEN SEGMENT DECODER TO DISPLAY NAME & REG NO
Public
project.name

homework 32:1 using 4:1 mux

homework 32:1 using 4:1 mux
Public
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COMMON CATHODE WITHOUT DON'T CARE

COMMON CATHODE WITHOUT DON'T CARE
Public
project.name

Design 16:4 Encoder using 4:2 Encoder

Design 16:4 Encoder using 4:2 Encoder
Public
project.name

4:16 decoder using 3:8

4:16 decoder using 3:8
Public
project.name

DLCD TASK3 16:1 MUX

DLCD TASK3 16:1 MUX
Public
project.name

MAG COMPARATOR Q9

MAG COMPARATOR Q9
Public
project.name

3:8 DECODER USING 2:4 DECODER

3:8 DECODER USING 2:4 DECODER
Public
project.name

74LS194 TASK 5

74LS194 TASK 5
Public
project.name

3*8 decoder using 2*4

3*8 decoder using 2*4
Public
project.name

3:8 DECODER USING 2:4 DECODER

3:8 DECODER USING 2:4 DECODER
Public
project.name

4:16 decoder using 2:4 decoders

4:16 decoder using 2:4 decoders
Public
project.name

Mid-Term Assignment

Mid-Term Assignment
Public
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COMMON CATHODE with / without DON'T CARE

COMMON CATHODE with / without DON'T CARE
Public
project.name

Experiment 12 : Verification of truth table of 4 bit bidirectional shift register

Experiment 12 : Verification of truth table of 4 bit bidirectional shift register
Public
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COMMON CATHODE with/without DON'T CARES [ 1:16 DE-MULTIPLEXER ]

COMMON CATHODE with/without DON'T CARES [ 1:16 DE-MULTIPLEXER ]
Public
project.name

CAT 2 Q2

CAT 2 Q2
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CAT 2 Q3

CAT 2 Q3
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project.name

CAT 2 Q3

CAT 2 Q3
Public
project.name

CAT 2 Q4

CAT 2 Q4
Public
project.name

CAT 2 Q8

CAT 2 Q8
Public
project.name

4:16 decoder using 2:4 decoders

4:16 decoder using 2:4 decoders
Public
project.name

PARALLEL ADDER Q8 DA 1

PARALLEL ADDER Q8 DA 1
Public
project.name

COMMON ANODE with/without DON'T CARES [1:16 DE-MULTIPLEXER]

COMMON ANODE with/without DON'T CARES [1:16 DE-MULTIPLEXER]
Public
project.name

CAT 2 Q5 - 4:16 Decoder using NOR logic.

CAT 2 Q5 - 4:16 Decoder using NOR logic.
Public
project.name

COMMON ANODE WITH DON'T CARES 16:1 MUX

COMMON ANODE WITH DON'T CARES 16:1 MUX
Public
project.name

32 to 1 mux using 4 to 1 mux

32 to 1 mux using 4 to 1 mux
Public
project.name

CAT 1 Q4

CAT 1 Q4
Public
project.name

COMMON ANODE WITH DON'T CARES 16:1 MUX

COMMON ANODE WITH DON'T CARES 16:1 MUX
Public
project.name

Design 16:4 Encoder using 4:2 Encoder

Design 16:4 Encoder using 4:2 Encoder
Public
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4 bit PIPO shift Register

4 bit PIPO shift Register
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Experiment 8

Experiment 8
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