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Incubated From:
Author: Connor Cieslinski
Forked from: Linggeis Daran/CSA 24927 LAB 3 8 x 16-bit Register File for RISC-V CPU
Project access type: Public
Description:
The design of a Register File with single-write port and dual-read ports following the design specification of RISC-V (RV16I).
Created: Sep 28, 2020
Updated: Sep 28, 2020
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