CSA 24927 LAB 3 8 x 16-bit Register File for RISC-V CPU
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Author: Linggeis Daran

Project access type: Public

Description:

The design of a Register File with single-write port and dual-read ports following the design specification of RISC-V (RV16I).

Created: Jul 01, 2020

Updated: Jun 30, 2023


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