YABEI SAP System
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Author: AD supercomputer

Forked from: Derek Wheeler/YABEI SAP System

Project access type: Public

Description:

Yet Another Ben Eater Inspired Simple As Possible System

I'm following along with the excellent YouTube instructional series Building an 8-bit breadboard computer! by Ben Eater.

Note that he credits the book "Digital Computer Electronics" by Albert Paul Mauvino for many of the SAP (Simple As Possible) ideas.

I'm mostly keeping it the same as his computer except:

  • I decided to have an 8-bit address space rather than 4-bits. 
  • Indirect mode instructions require another register.
  • Instructions only take as many clock cycles as they need as opposed to each instruction taking the same number of cycles and shorter instructions wasting the leftover cycles.
  • I didn't implement the hex or digital multi-segment displays... man that looked tedious!
  • I ended up having to do the microcode using combinational logic rather than EEPROM as the circuitverse EEPROM currently only supports 8 address lines and I needed at least 10

10/31/2020 - Only supports 2 op codes! LDA immediate and indirect

11/02/2020 - Added a few new opcodes. Added the Flags register. Rewrote the Control Unit using conditional logic rather than EEPROM. Fixed reset logic to properly reset PC to zero rather than whatever was currently on the bus.

11/03/2020 - Instruction Cycle Counter now resets as the last cycle of each opcode. So each opcode only takes as many clock cycles as it needs... like a normal CPU!

11/07/2020 - Added JZ (immediate) opcode. Added new sample program that uses it.

11/17/2020 - Added STA (immediate) and SUB (immediate) opcodes

11/18/2020 - Added HLT opcode. Implemented memory map: 0-247 are EEPROM, 248-255 are RAM

11/22/2020 - Added ADD (indirect) opcode. Changed default program to a Fibonacci sequence program

Created: Nov 25, 2020

Updated: Aug 26, 2023


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