CircuitVerse - 2-Cycle RISC CPU

2-Cycle RISC CPU

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Author: Abc Bcd

Forked from: Edward Searls/2-Cycle RISC CPU

Project access type: Public

Description:

This is an updated version of a CPU I designed for a class called Computer Architecture. It operates with a subset instruction set of RISC-V where each instruction can be implemented in 2-cycles.

Created: Dec 07, 2024

Updated: Dec 07, 2024

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