A complete 8-bit CPU starting from a nand for the students of Telecom SudParis/Institut Polytechnique de Paris. You can find the lab 

here: https://www-inf.telecom-sudparis.eu/cours/CSC4536/web/?page=TPs/logic/logic&soluce=true.

The processor consists in:

• 8 8-bits registers
• A ROM of 32 bytes and a RAM of 256 bytes. Addresses from 0 to 31 goes to the ROM, the others to the RAM
• A simple instruction set inspired by MIPS (lw, sw, addiu, addu, etc...)

• nand and nand-cc: to explain how we use circuitverse (optional)
• gates: to understand how we can build the gates (optional)
• half-add, 1-add, 4-add: step by step implementation of a (4 bits) adder (optional)
• 1x1-mux, 1x2-mux, 2x2-mux: step by step implementation of a (2x2bits) multiplexers (optional)
• mod5: as the name suggest, compute a modulo 5
• ALU: a simple ALU only able to execute add (required)
• SR-nand, JK-flip-flop, half-D-flip-flop, D-flip-flop-initial, D-flip-flop: step by step implementation of a (one bit) D-flip-flop
• 2x1-demux: a 1-bit demultiplexer with 4 outputs (optional)

• REGS: a helper that simplifies the use of a register
• CLOCK: a better clock useful for debugging. 
• CPUv0: a circuit that connects REGS and CLOCK
• MINI-PC: a circuit that performs an increment module 5. Used for the loop that fetches the instructions from memory. 
  
• CPUv1: integrate MINI-PC in CPUv0
• ENCODER: a helper circuit able to compute the value of an instruction from simple inputs
  
• MICROCODE: the microcode used by the processor (a loop that (i) loads the first 8-bytes of the instruction in %insnl, increments PC, loads the next 8 bytes in %insnh, increments PC and executes the instruction)
• CPUv2: integrate MICROCODE in CPUv1
• CPUv3: add a memory to CPUv2
• CPUv4: add ALU to CPUv3
• DECODER: instruction decoder
• CPU: the final CPU. Technically CPUv4 with DECODER.

The CPU executes the code "char x; while(true) x++;" where x is located at address 0x80. In details, the CPU executes this code, which is located in ROM:

•   li %r1, 0x80.     /* implemented with addiu %r0, 0x80 */
• lab:
•   lw %r0, (%r1)
•   addiu %r0, 1
•   sw %r0, (%r1)
•   br lab             /* implemented with addiu %pc, -8 */