[CSCA] Register Transfer and Bus Systems
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Author: Marcel Borkowski

Forked from: Igor Rončević/[CSCA] Register Transfer and Bus Systems

Project access type: Public

Description:

Register transfer methods and bus systems discussed in the Computer Science and Computer Architectures [CSCA] course at the University of Applied Sciences CAMPUS 02, Graz, Austria.

The project features the following circuits:

  • 4-Bit Register - reusable sub-circuit developed by using D flip-flops, and used as register element in other circuits.
  • Many-to-One Register Transfer - demonstrates transferring content from several source registers to a single target register via multiplexer.
  • One-to-Many Register Transfer - demonstrates transferring content from a single source register to several target registers via decoder.
  • Common Bus System (Isolated) - demonstrates a common bus system isolated from external inputs.
  • Common Bus System (With Initial Input) - demonstrates a common bus system with external input used to initially load content into registers.
  • Common Bus System (Registers and RAM) - demonstrates a common bus system used to transfer content between registers and RAM.

Created: Jan 20, 2023

Updated: Aug 27, 2023


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