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Author: Marcel Borkowski
Forked from: Igor Rončević/[CSCA] Counters and Timing Signals
Project access type: Public
Description:
Counters and timing signal generators discussed in the Computer Science and Computer Architectures [CSCA] course at the University of Applied Sciences CAMPUS 02, Graz, Austria.
The project features the following circuits:
Created: Jan 22, 2023
Updated: Aug 27, 2023
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