ENG103Digital Electronics DesignLab Experiment 6 (Online Simulator)Designing Sequential Circuit Using JK FFName of the Candidate:Student PI No. : LAB Experiment 6 – Designing Sequential Circuit Using JK Flip-flops____________________________________________________________________________
ENG103 Lab Expt 6 SINGAPORE UNIVERISTY OF SOCIAL SCIENCES (SUSS) Page 2 of 5OBJECTIVES: To appreciate the concepts of State diagram and State table.To design sequential circuit using JK flip-flops and combinational logic circuits.To use DeMorgan’s Theorem to construct the combinational logic part of the circuit using only NOR gates.To wire up the sequential circuit using online simulator CircuitVerse. (https://circuitverse.org/)In this experiment, you are provided with the circuit diagram of an unknown circuit. Given the following expressions for the J’s and K’s input, draw the circuit diagram for the Next State Forming Combinational Circuit block shown in Figure E6. You must use the minimum number of the 2-inputs NOR gates only.1.First, you must derive the Boolean functions of the state-decoding logics. Using DeMorgan’s Theorem, redesign the combinational logic part of the circuit, to replace
ENG103 Lab Expt 6 SINGAPORE UNIVERISTY OF SOCIAL SCIENCES (SUSS) Page 3 of 5the AND gates and OR gates with NOR gates only. Show your new Boolean expressions.New NOR only Booleans:
ENG103 Lab Expt 6 SINGAPORE UNIVERISTY OF SOCIAL SCIENCES (SUSS) Page 4 of 52.Implement the circuit with JK flip-flops and 2-inputs NOR gates only using the online simulator. Probe the clock, QA, QB, and QC timing signals. Screen captures the circuit and show it below.
ENG103 Lab Expt 6 SINGAPORE UNIVERISTY OF SOCIAL SCIENCES (SUSS) Page 5 of 53.Observe the various states of the circuit and record all possible states of the circuits in Table E6. You may need to apply a slower clock signal. To get to the unused state, you will need to disable the clock and preset the filp-flops to the unused states first before reapplying the clock pulse. The clock could be enabled or disabled in the project properties. Async RESET and PRESET are used to preset the flip-flops.Table E6Current StateQAQBQCNext StateQAQBQC0001000010000100100110011001101011011101111110114.Screen captures the timing diagram for the clock, QA, QB, and QC below, showing all the possible transition states.5.Draw a state diagram for this circuit and state the function of the circuit.----- END OF EXPERIMENT -----ENG103 Lab Expt 6 SINGAPORE UNIVERISTY OF SOCIAL SCIENCES (SUSS) Page 5 of 53.Observe the various states of the circuit and record all possible states of the circuits in Table E6. You may need to apply a slower clock signal. To get to the unused state, you will need to disable the clock and preset the filp-flops to the unused states first before reapplying the clock pulse. The clock could be enabled or disabled in the project properties. Async RESET and PRESET are used to preset the flip-flops.Table E6Current StateQAQBQCNext StateQAQBQC0001000010000100100110011001101011011101111110114.Screen captures the timing diagram for the clock, QA, QB, and QC below, showing all the possible transition states.5.Draw a state diagram for this circuit and state the function of the circuit.
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