De Morgan's Law
De Morgan's Law
Untitled
UntitledThe activity is to display the first 8 valid characters of your name without repetition of same display.
4 bit adder
4 bit adderDigital Design, CPU Design, ALU Design for Class Project
CPU V1.0
CPU V1.0Digital Design, CPU Design, ALU Design
Tryte-ALU
Tryte-ALUDesign and implementation of a Tryte-Based Arithmetic Logic Unit (ALU) leveraging unbalanced ternary logic for advanced computation. The project aims to explore efficient ternary operations, utilizing Tryte (3-trit) structures for processing, and integrating scalable digital design principles. The ALU is designed for simulation and synthesis in CircuitVerse with Verilog HDL.
