Debajyoti Jana
Member since: 3 years
Educational Institution: Not Entered
Country: Not Entered
mux
mux
Public
4 Bit Synchronous Up Down Counter
4 Bit Synchronous Up Down Counter
Public
BIDIRECTIONAL REGISTER
BIDIRECTIONAL REGISTER
Public
MOD 5 Asynchronous Up Counter
MOD 5 Asynchronous Up Counter
Public
4 Bit Synchronous Up Down Counter
4 Bit Synchronous Up Down Counter
Public
Full Subtractor
Full Subtractor
Public
synchronous up and down counter using mux
synchronous up and down counter using mux
Public
FULL SUBTRACTOR USING NOR GATE
FULL SUBTRACTOR USING NOR GATE
Public
4 Bit Right and Left Shift Register
4 Bit Right and Left Shift Register
Public
8:1 Mux using Logic Gates
8:1 Mux using Logic Gates
Public
Full ADDER
Full ADDER
Public
J K
J K
Public
J K
J K
Public
BIDIRECTIONAL REGISTER
BIDIRECTIONAL REGISTER
Public
SHIFT REGISTER
SHIFT REGISTER
Public
4:1 MUX
4:1 MUX
Public
MUX 4:1
MUX 4:1
Public
DESIGN AND REALIZATION OF FULL ADDER AND FULL SUBTRACTOR CIRCUITS
DESIGN AND REALIZATION OF FULL ADDER AND FULL SUBTRACTOR CIRCUITS
Public
SR
SR
Public
MOD 4 ASYNCHRONOUS DOWN COUNTER
MOD 4 ASYNCHRONOUS DOWN COUNTER
Public
Full Subtractor using NOR Gates
Full Subtractor using NOR Gates
Public
synchronous up and down counter using mux
synchronous up and down counter using mux
Public
4x1 Multiplexer
4x1 Multiplexer
Public
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