Member since: 491 days
Educational Institution: Ajay Kumar Garg Engineering College ,Ghaziabad
Country: India
Half Adder
Half AdderFlip Flops
Flip Flopsexp-7 DATA PATH OF COMPUTER FROM IT
exp-7 DATA PATH OF COMPUTER FROM ITEXP-6 8-BIT I/O with 4x 8-BIT Internal REG.
EXP-6 8-BIT I/O with 4x 8-BIT Internal REG.3x8 Decoder
3x8 DecoderFull Adder using 2 x Half Adder
Full Adder using 2 x Half Adder4x1 MUX
4x1 MUXBinary To Gray (4 BIT)
Binary To Gray (4 BIT)