Aadarsh Pandey
Member since: 277 days
Educational Institution: Ajay Kumar Garg Engineering College ,Ghaziabad
Country: India
Half Adder
Half Adder
Public
Flip Flops
Flip Flops
Public
exp-7 DATA PATH OF COMPUTER FROM IT
exp-7 DATA PATH OF COMPUTER FROM IT
Public
EXP-6 8-BIT I/O with 4x 8-BIT Internal REG.
EXP-6 8-BIT I/O with 4x 8-BIT Internal REG.
Public
3x8 Decoder
3x8 Decoder
Public
4x1 MUX
4x1 MUX
Public
Full Adder using 2 x Half Adder
Full Adder using 2 x Half Adder
Public
Binary To Gray (4 BIT)
Binary To Gray (4 BIT)
Public
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