project.name

Aadarsh Pandey

Member since: 3 years

Educational Institution: Ajay Kumar Garg Engineering College ,Ghaziabad

Country: India

Half Adder

Half Adder
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Flip Flops

Flip Flops
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3x8 Decoder

3x8 Decoder
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Full Adder using 2 x Half Adder

Full Adder using 2 x Half Adder
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4x1 MUX

4x1 MUX
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EXP-6 8-BIT I/O with 4x 8-BIT Internal REG.

EXP-6 8-BIT I/O with 4x 8-BIT Internal REG.
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exp-7 DATA PATH OF COMPUTER FROM IT

exp-7 DATA PATH OF COMPUTER FROM IT
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Binary To Gray (4 BIT)

Binary To Gray (4 BIT)
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