Putu Widyantara Artanta Wibawa
Member since: 3 years
Educational Institution: Udayana University
Country: Indonesia
F = A’ + (B.C’) + (A’.B’)
F = A’ + (B.C’) + (A’.B’)
Register
Register
F=((A'.A') + A) (B .((B’.C)+C’))
F=((A'.A') + A) (B .((B’.C)+C’))
Decoder
Decoder
Encoder
Encoder
Decoder 3 to 8
Decoder 3 to 8
Asynchronous Up Counter + 7 Segment
Asynchronous Up Counter + 7 Segment
ADDER / SUBTRACTER
ADDER / SUBTRACTER
D-LATCH WITH ENABLE USING "AND" GATES
D-LATCH WITH ENABLE USING "AND" GATES
SOAL 3 - TUGAS PRAKTIKUM 3
SOAL 3 - TUGAS PRAKTIKUM 3
(A+A).(A+B).(B+B)+A(A+B)+B(B+A)
(A+A).(A+B).(B+B)+A(A+B)+B(B+A)
Counter
Counter
E_2108561005_Putu Widyantara Artanta Wibawa_Pendahuluan 3
E_2108561005_Putu Widyantara Artanta Wibawa_Pendahuluan 3
Q = A(ABC + AB’C + A’BC + ABC’)
Q = A(ABC + AB’C + A’BC + ABC’)
SYNCHRONOUS UP MOD 10 COUNTER
SYNCHRONOUS UP MOD 10 COUNTER
Soal 2 - Tugas Praktikum 6
Soal 2 - Tugas Praktikum 6
Q = A(A+B’+C’) + A(A’B+BC)
Q = A(A+B’+C’) + A(A’B+BC)
PLEXER
PLEXER
Q = (A+B+C)’ (A+B+C’)’ (A’+B+C’)’
Q = (A+B+C)’ (A+B+C’)’ (A’+B+C’)’
FINAL PROJECT PRAKSISDIG GANJIL
FINAL PROJECT PRAKSISDIG GANJIL
E_2108561005_Putu Widyantara Artanta Wibawa_Pendahuluan 5
E_2108561005_Putu Widyantara Artanta Wibawa_Pendahuluan 5
F = AB + ((B+C)(BC))
F = AB + ((B+C)(BC))
F = A . (B + C’) . (A’ + C)
F = A . (B + C’) . (A’ + C)
Q = X'YZ + XYZ +XY'Z +XYZ'
Q = X'YZ + XYZ +XY'Z +XYZ'
FLIP-FLOP
FLIP-FLOP
Half Adder
Half Adder
NOR-Latch
NOR-Latch
NAND-Latch
NAND-Latch
POS soal 4
POS soal 4
SOP soal 4
SOP soal 4
SOP soal 4 NOR
SOP soal 4 NOR
POS soal 4 NAND
POS soal 4 NAND
