project.name

vijayesh

Member since: 3 years

Educational Institution: Not Entered

Country: Not Entered

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gray to binary
Public
project.name

binary to gray

binary to gray
Public
project.name

jk flip flop

jk flip flop
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rs latch

rs latch
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d flip flop

d flip flop
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ese2

ese2
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dcf practical before and after

dcf practical before and after
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half adder

half adder
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full adder

full adder
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practical 2

practical 2
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practical 1

practical 1
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A(B+CD)

A(B+CD)
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A(B+C+D)

A(B+C+D)
Public
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(A+B)(A+C)

(A+B)(A+C)
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A+(B+C+D)

A+(B+C+D)
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A+AB

A+AB
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A+A'B

A+A'B
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Untitled

Untitled
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AB+BCD+AC

AB+BCD+AC
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OR GATE

OR GATE
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NOT

NOT
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AB' + A'B'

AB' + A'B'
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AB + A(B+C)

AB + A(B+C)
Public
project.name

A'B + A'B C+A B'+ A B'D (with NAND Gate only)

A'B + A'B C+A B'+ A B'D (with NAND Gate only)
Public
project.name

AB + A(B+C) + D

AB + A(B+C) + D
Public
project.name

AB + BC(B + C)

AB + BC(B + C)
Public
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Untitled

Untitled
Public
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Untitled

Untitled
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AB+A(B+C)+B(B+C)

AB+A(B+C)+B(B+C)
Public
project.name

rs flip flop

rs flip flop
Public
project.name

A(A' +AB)

A(A' +AB)
Public
project.name

Untitled

Untitled
Public
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project.name