project.name

Vaibhav Gupta

Member since: 3 years

Educational Institution: Ajay Kumar garg engineering college

Country: India

D flip flop

D flip flop
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SR flip flop

SR flip flop
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decoder

decoder
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8:1 Mux using Logic Gates

8:1 Mux using Logic Gates
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ALU

ALU
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4-bit asynchronus counter

4-bit asynchronus counter
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8 bit ALU

8 bit ALU
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n bit counter

n bit counter
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JK flip flop

JK flip flop
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gray to binary 8 bit

gray to binary 8 bit
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Multiplexer

Multiplexer
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4 Bit Carry Look Ahead Adder

4 Bit Carry Look Ahead Adder
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binary to gray 8 bit

binary to gray 8 bit
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binary to gray 4 bit

binary to gray 4 bit
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3 TO 8 LINE DECODER

3 TO 8 LINE DECODER
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Register to Bus Transfer

Register to Bus Transfer
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4 Bit Carry Look Ahead Adder

4 Bit Carry Look Ahead Adder
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4*1 multiplexers

4*1 multiplexers
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T flip flop

T flip flop
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8 bit input output

8 bit input output
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SAP - 1

SAP - 1
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