project.name

Gauri Dhingra

Member since: 2 years

Educational Institution: Not Entered

Country: India

complete ALU

complete ALU
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Half Adder using Half Subtractor

Half Adder using Half Subtractor
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Exp-8 To simulate the logical part of a simple ALU

Exp-8 To simulate the logical part of a simple ALU
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LOGICAL SHIFT

LOGICAL SHIFT
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Exp-7 Common bus using 4X1 MUX

Exp-7 Common bus using 4X1 MUX
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Complete ALU

Complete ALU
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BCD

BCD
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Exp-6 Tri State Buffer

Exp-6 Tri State Buffer
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Complete ALU

Complete ALU
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EXP7.-COMMON BUS USING 4X1 MUX

EXP7.-COMMON BUS USING 4X1 MUX
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Exp5(i)

Exp5(i)
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Common Bus using tri state buffer

Common Bus using tri state buffer
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Exp-6 To simulate a common bus using tri-state buffer using demux

Exp-6 To simulate a common bus using tri-state buffer using demux
Public
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ALU LOGIC

ALU LOGIC
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4 bit bcd adder

4 bit bcd adder
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Exp-6: To simulate a common bus using tri-state buffer

Exp-6: To simulate a common bus using tri-state buffer
Public
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Arithmetic logical Unit

Arithmetic logical Unit
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