project.name

SNEHA MAURYA

Member since: 3 years

Educational Institution: Not Entered

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flipflop 2

flipflop 2
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Untitled

Untitled
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Untitled

Untitled
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Untitled

Untitled
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bus

bus
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data path

data path
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alu

alu
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4 Bit Carry Look ahead adder

4 Bit Carry Look ahead adder
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4-bit-carry-lookahead-adder

4-bit-carry-lookahead-adder
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4*1 multiplexers

4*1 multiplexers
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4*1 multiplexers

4*1 multiplexers
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8:1 Mux using Logic Gates

8:1 Mux using Logic Gates
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8 bit input output

8 bit input output
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D flip flop

D flip flop
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8 bit ALU

8 bit ALU
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4 Bit Carry Look Ahead Adder

4 Bit Carry Look Ahead Adder
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SR flip flop

SR flip flop
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T flip flop

T flip flop
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JK flip flop

JK flip flop
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gates implementation

gates implementation
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gates implementation

gates implementation
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binary to gray 8 bit

binary to gray 8 bit
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T flip flop

T flip flop
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4-bit asynchronus counter

4-bit asynchronus counter
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gray to binary 8 bit

gray to binary 8 bit
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experiment 2

experiment 2
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SR flip flop

SR flip flop
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experiment 1

experiment 1
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3:8 Decoder

3:8 Decoder
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3 TO 8 LINE DECODER

3 TO 8 LINE DECODER
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D flip flop

D flip flop
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Untitled

Untitled
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SNEHA MAURYA is not a collaborator of any project.

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