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Data path
Data pathData path
Data pathData path
Data pathData path
Data pathData path
Data pathData path
Data pathCLA
CLA4 bit counters
4 bit countersgray to binary 8 bit
gray to binary 8 bit4*1 multiplexers
4*1 multiplexersExperiment 1
Experiment 13 to 8 line decoder
3 to 8 line decoder8-bit register
8-bit registerSR flip flop
SR flip flop8 bit input output
8 bit input output8 bit ALU
8 bit ALUHalf addder using basic gates
Half addder using basic gatesExperiment 2
Experiment 23 to 8 line decoder
3 to 8 line decoderCLA
CLA8-bit register
8-bit registerFull adder using basic gates
Full adder using basic gatesTesting of various gates
Testing of various gates4-bit asynchronus counter
4-bit asynchronus counterBinary to gray code converter
Binary to gray code converterD Flip-Flop
D Flip-FlopTesting of various gates
Testing of various gatesData path
Data path8:1 Mux using Logic Gates
8:1 Mux using Logic Gates4 Bit Carry Look Ahead Adder
4 Bit Carry Look Ahead AdderTesting of various gates
Testing of various gatesT Flip Flop
T Flip FlopJK flip flop
JK flip flopJK Flip flop
JK Flip flopD flip flop
D flip flopbinary to gray 8 bit
binary to gray 8 bit8 bit input output system with four 8-bit internal registers
8 bit input output system with four 8-bit internal registersClocked SR Flip Flop
Clocked SR Flip FlopT flip flop
T flip flopTesting of various gates
Testing of various gates