4-bit asynchronus counter

T flip flop

4 Bit Carry Look Ahead Adder

Sharanya200270100142

D Flip Flop

SR Flip Flop

SR Flip Flop

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path

path

8 bit ALU

Binary to Gray

SR flip flop

D flip flop

8 bit ALU

PATH TRANSFER

Verify the excitation tables of various FLIP-FLOPS.

8 bit input output

16 : 1 Multiplexer

MUX using universal gates

Sharanya bajpai/Verify the excitation tables of various FLIP-FLOPS.

Sharanya bajpai/Verify the excitation tables of various FLIP-FLOPS.

8 BIT ALU

Sharanya bajpai/Verify the excitation tables of various FLIP-FLOPS.

JK flip flop

Exp. No. 1 :- Implementing Half Adder and Full Adder using basic logic gates

Implement 4-bit Gray-to-Binary code converter.

Pratham Maheshwari/ Implementing 3-8 line DECODER and Implementing 4x1 and 8x1 MULTIPLEXERS.

Verify the excitation tables of various FLIP-FLOPS.

ALU

8 : 1 Multiplexer (alternative)

8 : 1 Multiplexer (alternative)

Experiment9(15/10/2020)

4X1 MUX using Basic Gates

Implementing 3-8 line DECODER and Implementing 4x1 and 8x1 MULTIPLEXERS.