From https://en.wikipedia.org/wiki/Flip-flop_(electronics)#SR_AND-OR_latch

If Reset is high, then the inverter makes Not Reset low, which forces the output of the AND gate to be low, making both the output Q and the Stored Bit Of Data low.

If Reset is low, then the inverter makes Not Reset high, and the AND gate can pass through the output of the OR gate.

If Set is high, then the OR gate will pass the high signal through the AND gate to the output Q, and that high will be saved in the Stored Bit Of Data, which feeds back into the OR gate, maintaining that bit's state.

If Set goes from high to low and Reset is and remains low, the circuit will maintain the output Q high.