project.name

Hirnaymay Bhaskar

Member since: 503 days

Educational Institution: Ajay Kumar Garg Engineering College

Country: India

Experiment - 6: ALU

Experiment - 6: ALU
Public
Experiment - 6: ALU

Experiment - 0: Basic Gates

Experiment - 0: Basic Gates
Public
Experiment - 0: Basic Gates

Experiment - 1: Full Adder with basic Gates

Experiment - 1: Full Adder with basic Gates
Public
Experiment - 1: Full Adder with basic Gates

Experiment - 3: Decoder and Multiplexer

Experiment - 3: Decoder and Multiplexer
Public
Experiment - 3: Decoder and Multiplexer

Carry Look Ahead Adder

Carry Look Ahead Adder
Public
Carry Look Ahead Adder

Experiment - 7: Data Path

Experiment - 7: Data Path
Public
Experiment - 7: Data Path

counter

counter
Public
counter

Experiment - 2: Gray to Binary Converter

Experiment - 2: Gray to Binary Converter
Public
Experiment - 2: Gray to Binary Converter

Experiment 4 + 5: Flip Flop/ 8bits I/O

Experiment 4 + 5: Flip Flop/ 8bits I/O
Public
Experiment 4 + 5: Flip Flop/ 8bits I/O

Full Adder with Half Adder

Full Adder with Half Adder
Public
Full Adder with Half Adder
No result image
Hirnaymay Bhaskar is not a collaborator of any project.