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Hirnaymay Bhaskar

Member since: 2 years

Educational Institution: Ajay Kumar Garg Engineering College

Country: India

Experiment - 6: ALU

Experiment - 6: ALU
Public
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Experiment - 0: Basic Gates

Experiment - 0: Basic Gates
Public
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Experiment - 7: Data Path

Experiment - 7: Data Path
Public
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counter

counter
Public
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Experiment - 2: Gray to Binary Converter

Experiment - 2: Gray to Binary Converter
Public
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Experiment 4 + 5: Flip Flop/ 8bits I/O

Experiment 4 + 5: Flip Flop/ 8bits I/O
Public
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Full Adder with Half Adder

Full Adder with Half Adder
Public
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Carry Look Ahead Adder

Carry Look Ahead Adder
Public
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Experiment - 1: Full Adder with basic Gates

Experiment - 1: Full Adder with basic Gates
Public
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Experiment - 3: Decoder and Multiplexer

Experiment - 3: Decoder and Multiplexer
Public
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Hirnaymay Bhaskar is not a collaborator of any project.