SR Latch using NOR

SR Flip Flop with NAND

D Flip Flop

((A.B').(B.D +C) + (A'.B')).C

A.B + A.(B+C) + B.(B+C)

A’.B + A’.B.C’ +A’.B.C.D + A’.B.C.D + A’.B.C’.D’.E

A.B’ + A.(B+C)’ + B.(B + C)’

(A.B’ + B.(C’ + (C.D)’) )’

(A.B)' + (A.C)' + (A+B+C)'

NAND to OR

NAND to NOT

NAND to AND

NAND to NOR

NAND to XOR

NAND to XNOR

NOR to NOT

NOR to AND

NOR to AND

NOR to OR

NOR to XOR

Half Adder Sum

Simplified A Circuit

Simplified B Circuit

Simplified D

Simplified C Circuit

Simplified E Circuit

Simplified F Circuit

Simplified G Circuit

SR Latch using NAND