Member since: 3 years
Educational Institution: Ajay Kumar Garg Engineering College
Country: India
Experiment 4(T, D, SR, JK FLIP FLOP)
Experiment 4(T, D, SR, JK FLIP FLOP)Experiment 1 (Full)
Experiment 1 (Full)Experiment 1 (Half)
Experiment 1 (Half)Experiment 5 (input output system)
Experiment 5 (input output system)Experiment 7 (4 Bit Carry Look ahead adder)
Experiment 7 (4 Bit Carry Look ahead adder)Experiment 9( n bit counter)
Experiment 9( n bit counter)Experiment 5 (8 Bit Input Output System)
Experiment 5 (8 Bit Input Output System)Experiment 3 ( 3:8 Decoder, 8*1 Multiplexer)
Experiment 3 ( 3:8 Decoder, 8*1 Multiplexer)Exp. 2 (Gray to Binary, Binary To Gray)
Exp. 2 (Gray to Binary, Binary To Gray)Exp. 6 (1 Bit ALU)
Exp. 6 (1 Bit ALU)Data Path using MUX and decoder
Data Path using MUX and decoder