Anushka Debnath
Member since: 2 years
Educational Institution: Not Entered
Country: Not Entered
Analog
Analog
Analog
Analog
k
k
Analog
Analog
Analog
Analog
logic gates
logic gates
Untitled
Untitled
Untitled
Untitled
half adder
half adder
3:8 Decoder
3:8 Decoder
3:8 Decoder
3:8 Decoder
EXPERIMENT 6 - DESIGN AND SIMULATE A RIPPLE CARRY ADDER
EXPERIMENT 6 - DESIGN AND SIMULATE A RIPPLE CARRY ADDER
DESIGN AND SIMULATE A RIPPLE CARRY ADDER
DESIGN AND SIMULATE A RIPPLE CARRY ADDER
EXPERIMENT 8 - (A) DESIGN AND SIMULATE A 2:1 MUX, (B) CASCADE THREE 2:1 MUXs TO DESIGN A 4:1 MUX
EXPERIMENT 8 - (A) DESIGN AND SIMULATE A 2:1 MUX, (B) CASCADE THREE 2:1 MUXs TO DESIGN A 4:1 MUX
EXPERIMENT 9 - DESIGN A LOGICAL UNIT WHICH WILL PERFORM 4 OPERATIONS AND,OR,NOT,XOR
EXPERIMENT 9 - DESIGN A LOGICAL UNIT WHICH WILL PERFORM 4 OPERATIONS AND,OR,NOT,XOR
DESIGN A LOGICAL UNIT WHICH WILL PERFORM 4 OPERATIONS AND,OR,NOT,XOR
DESIGN A LOGICAL UNIT WHICH WILL PERFORM 4 OPERATIONS AND,OR,NOT,XOR
EXPERIMENT 10 - DESIGN AND SIMULATE A 4-BIT ARITHMETIC UNIT
EXPERIMENT 10 - DESIGN AND SIMULATE A 4-BIT ARITHMETIC UNIT
EXPERIMENT 8 - (A) DESIGN AND SIMULATE A 2:1 MUX, (B) CASCADE THREE 2:1 MUXs TO DESIGN A 4:1 MUX
EXPERIMENT 8 - (A) DESIGN AND SIMULATE A 2:1 MUX, (B) CASCADE THREE 2:1 MUXs TO DESIGN A 4:1 MUX
EXPERIMENT 7 - DESIGN AND SIMULATE A 4-BIT BCD ADDER
EXPERIMENT 7 - DESIGN AND SIMULATE A 4-BIT BCD ADDER
EXPERIMENT 10 - DESIGN AND SIMULATE A 4-BIT ARITHMETIC UNIT
EXPERIMENT 10 - DESIGN AND SIMULATE A 4-BIT ARITHMETIC UNIT
logic gates
logic gates
logic gates
logic gates
class 2409
class 2409
class 2409
class 2409
exp1
exp1
HALF SUBTRACTOR
HALF SUBTRACTOR
full adder
full adder
half adder
half adder
EXPERIMENT 7 - DESIGN AND SIMULATE A 4-BIT BCD ADDER
EXPERIMENT 7 - DESIGN AND SIMULATE A 4-BIT BCD ADDER
DESIGN AND SIMULATE A 4-BIT BCD ADDER
DESIGN AND SIMULATE A 4-BIT BCD ADDER
EXPERIMENT 7 - DESIGN AND SIMULATE A 4-BIT BCD ADDER
EXPERIMENT 7 - DESIGN AND SIMULATE A 4-BIT BCD ADDER
Analog
Analog
