project.name

Subhjeet Biswas

Member since: 60 days

Educational Institution: Delhi University

Country: India

NAND as a Universal Gate

NAND as a Universal Gate
Public
NAND as a Universal Gate

Circuit Simplification 4

Circuit Simplification 4
Public
Circuit Simplification 4

Circuit Simplification 3

Circuit Simplification 3
Public
Circuit Simplification 3

Circuit simplification 2

Circuit simplification 2
Public
Circuit simplification 2

Half Adder

Half Adder
Public
Half Adder

Half Substractor

Half Substractor
Public
Half Substractor

Full Adder

Full Adder
Public
Full Adder

Full Substractor

Full Substractor
Public
Full Substractor

R-S (NAND)

R-S (NAND)
Public
R-S (NAND)

RS NOR clocked

RS NOR clocked
Public
RS NOR clocked

Revised RS (NOR Gate)

Revised RS (NOR Gate)
Public
Revised RS (NOR Gate)

RS NAND (clocked)

RS NAND (clocked)
Public
RS NAND (clocked)

Circuit Simplification 1K2

Circuit Simplification 1K2
Public
Circuit Simplification 1K2

Circuit Simplification 1

Circuit Simplification 1
Public
Circuit Simplification 1

Exp 1 simp2

Exp 1 simp2
Public
Exp 1 simp2

exp 2 (1)

exp 2 (1)
Public
exp 2 (1)

Ex 2 (2)

Ex 2 (2)
Public
Ex 2 (2)

Exp 2 (dont care 3)

Exp 2 (dont care 3)
Public
Exp 2 (dont care 3)
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