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Subhjeet Biswas

Member since: 2 years

Educational Institution: Delhi University

Country: India

Ex 2 (2)

Ex 2 (2)
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Circuit Simplification 1K2

Circuit Simplification 1K2
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Circuit Simplification 3

Circuit Simplification 3
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Circuit simplification 2

Circuit simplification 2
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R-S (NAND)

R-S (NAND)
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RS NOR clocked

RS NOR clocked
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Revised RS (NOR Gate)

Revised RS (NOR Gate)
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Exp 2 (dont care 3)

Exp 2 (dont care 3)
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SISO SF with D FF

SISO SF with D FF
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PISO SF by D FF

PISO SF by D FF
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Half Adder

Half Adder
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Circuit Simplification 4

Circuit Simplification 4
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Full Adder

Full Adder
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exp 2 (1)

exp 2 (1)
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Circuit Simplification 1

Circuit Simplification 1
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RS NAND (clocked)

RS NAND (clocked)
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Half Substractor

Half Substractor
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PIPO SF using D FF

PIPO SF using D FF
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NAND as a Universal Gate

NAND as a Universal Gate
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Full Substractor

Full Substractor
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Exp 1 simp2

Exp 1 simp2
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