project.name

NARALA SRINITHYA

Member since: 3 years

Educational Institution: Not Entered

Country: India

9920004580 end lab sipo

9920004580 end lab sipo
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De Morgan's theorem and distributive law

De Morgan's theorem and distributive law
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half,full adder and logic gates EX1&2

half,full adder and logic gates EX1&2
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7 Segment Display

7 Segment Display
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BCD 7 segment

BCD 7 segment
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EX4:COMBINATIONALCIRCUITS

EX4:COMBINATIONALCIRCUITS
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encoder and decoder

encoder and decoder
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PARITY CHECKERS AND GENERATORS

PARITY CHECKERS AND GENERATORS
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CODE CONVERTERS

CODE CONVERTERS
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SEQUENCIAL LOGIC CIRCUITS

SEQUENCIAL LOGIC CIRCUITS
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FULL AND HALF SUBTRACTER

FULL AND HALF SUBTRACTER
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{[(a+c')' * bd']' * [(a+c')*bd']' } ' ,kmap

{[(a+c')' * bd']' * [(a+c')*bd']' } ' ,kmap
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EX3:MAGNITUDE COMPARATOR

EX3:MAGNITUDE COMPARATOR
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SHIFT REGISTERS

SHIFT REGISTERS
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COUNTERS

COUNTERS
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half,full adder and logic gates EX1&2

half,full adder and logic gates EX1&2
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BCD 7 segment

BCD 7 segment
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