project.name

Preetha.R

Member since: 3 years

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Design and implementation of Half full adder and half/full subtrator

Design and implementation of Half full adder and half/full subtrator
Public
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Verfiication of Logic gate

Verfiication of Logic gate
Public
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THEOREMS

THEOREMS
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Exp 1. logic circuit

Exp 1. logic circuit
Public
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Verification of Logic Gate

Verification of Logic Gate
Public
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