project.name

SATRASALA VINAY KUMAR

Member since: 3 years

Educational Institution: KALASALINGAM UNIVERSITY

Country: India

PARITY

PARITY
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HALF ADDER AND FULL ADDER

HALF ADDER AND FULL ADDER
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De Morgan's theorom

De Morgan's theorom
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Distributive law

Distributive law
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SIMPLIFICATION OF LOGICGATES1

SIMPLIFICATION OF LOGICGATES1
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K MAP 1

K MAP 1
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comparator- 2 input

comparator- 2 input
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SUBTRACTORS

SUBTRACTORS
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BCD TO SEVEN SEGMENT DECODER

BCD TO SEVEN SEGMENT DECODER
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Flip-Flops using NAND Gate

Flip-Flops using NAND Gate
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Flip-Flops

Flip-Flops
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ENCODERS AND DECODERS

ENCODERS AND DECODERS
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combinational logic circuit-multiplexer

combinational logic circuit-multiplexer
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Code converter

Code converter
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implementation of logic gates

implementation of logic gates
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sequential logic circuits

sequential logic circuits
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SHIFT REGISTERS

SHIFT REGISTERS
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combinational logic circuit-demultiplexer

combinational logic circuit-demultiplexer
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Ring and Johnson Counter

Ring and Johnson Counter
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