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PASALA SAI KUMAR REDDY CSEUG-2020 Batch

Member since: 3 years

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De Morgan's theorom

De Morgan's theorom
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Distributive law

Distributive law
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HALF ADDER AND FULL ADDER

HALF ADDER AND FULL ADDER
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SIMPLIFICATION OF LOGICGATES1

SIMPLIFICATION OF LOGICGATES1
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K MAP 1

K MAP 1
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combinational logic circuit-multiplexer

combinational logic circuit-multiplexer
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combinational logic circuit-demultiplexer

combinational logic circuit-demultiplexer
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gray code to binary

gray code to binary
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sequential logic circuits

sequential logic circuits
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HALF AND FULL ADDER

HALF AND FULL ADDER
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SUBTRACTORS

SUBTRACTORS
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encoder

encoder
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decoder

decoder
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PARITY

PARITY
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SISO

SISO
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SIPO

SIPO
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implementation of logic gates

implementation of logic gates
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2-bit ripple counter

2-bit ripple counter
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comparator- 2 input

comparator- 2 input
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BCD TO SEVEN SEGMENT DECODER

BCD TO SEVEN SEGMENT DECODER
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MODEL LAB

MODEL LAB
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binary to gray code converter

binary to gray code converter
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PASALA SAI KUMAR REDDY CSEUG-2020 Batch is not a collaborator of any project.

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