project.name

Abhishek Rajput

Member since: 3 years

Educational Institution: Not Entered

Country: Not Entered

ASSESSMENT

ASSESSMENT
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Assessment

Assessment
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full adder

full adder
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ALL GATES USING NAND GATE

ALL GATES USING NAND GATE
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ALL GATES USING NOR GATE

ALL GATES USING NOR GATE
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half adder

half adder
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FULL ADDER USING FULL SUBTRACTOR

FULL ADDER USING FULL SUBTRACTOR
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ALU LOGIC

ALU LOGIC
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AND

AND
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NAND

NAND
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NOR

NOR
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XOR

XOR
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XNOR

XNOR
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AND using NAND

AND using NAND
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Untitled

Untitled
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complete ALU

complete ALU
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Half adder using half subtractor

Half adder using half subtractor
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4 bit bcd adder

4 bit bcd adder
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OR

OR
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Untitled

Untitled
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full subtractor usig nand gate only

full subtractor usig nand gate only
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Tic tac toe Simulator

Tic tac toe Simulator
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ALL GATES USING NOR GATE

ALL GATES USING NOR GATE
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adder subtractor

adder subtractor
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