even parity generator exp 13 a

exp 19 Realization of the internal architecture of 3:8 Decoder using basic gates

EXP 18 Realization of 4:2 Priority Encoder along with output indicator (Basic Gates).

exp 11 full subtractor

PARITY CHECKER exp 13 b

Full Subtractor

GRAY TO BINARY(EXP-5)

EXP 6(BCD to EXCESS 3)

exp 2

exp 3

exp 16

EXP 1 B

XOR using NOR

Experiment 9

half subtractor exp 10

EXP 12FULL SUBTRACTOR USING TWO HALF SUBTRACTOR

4:1 MUX exp 15 a

FULL ADDER(EXP-8B)

HALF ADDER(EXP-8A)

1:4DEMUX(EXP-15B)

s flip flop nand gate(EXP 22)

t flip flop nand gate(EXP 24)

SISO

NOT USING NAND

NOT USING NOR

AND USING NAND

SIPO

AND USING NOR

XOR USING NAND

OR USING NAND

4:1 MUX EXP 15 A

pipo

2-BIT COMPARATOR exp 14

2-BIT COMPARATOR EXP 14

parity 12

BINARY TO GRAY(EXP-4)

SR flip flop nand gate (EXP 21)

EXP 7(EXCESS-3 TO BCD)

octal to binary (EXP 20)

OR USING NOR

(Exp 16) Implementation of Full Adder using MUX IC 4539B (4:1 MUX)

4 bit Synchronous DOWN Counter

EXP 12 FULL SUBTRACTOR USING TWO HALF SUBTRACTOR

1-BIT COMPARATOR

4-Bit Synchronous Up Counter

jk flip flop nand gate(EXP 23)

(Exp 17)Implementation of Full Subtractor using MUX IC 4539B (4:1 MUX).