Shashank Chowdhury
Member since: 3 years
Educational Institution: Kalasalingam university
Country: India
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Public
EX.NO:1 Implementation of Logic Gates
EX.NO:1 Implementation of Logic Gates
Public
PISO SHIFT REGISTER
PISO SHIFT REGISTER
Public
Flip-Flops
Flip-Flops
Public
MUX 1:4
MUX 1:4
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demux 1:4
demux 1:4
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1:8 mux
1:8 mux
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Encoder
Encoder
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decoder
decoder
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parity generator
parity generator
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parity check
parity check
Public
Flip Flops
Flip Flops
Public
2 bit magnitude comparator
2 bit magnitude comparator
Public
Binary to Grey And Grey to Binary
Binary to Grey And Grey to Binary
Public
Parallel in Parallel Out Shift Register
Parallel in Parallel Out Shift Register
Public
Counter
Counter
Public
4-bit ripple counter
4-bit ripple counter
Public
Full adder using NAND Gate
Full adder using NAND Gate
Public
Binary to excess 3
Binary to excess 3
Public
half Subtractor
half Subtractor
Public
JK flip flop using NAND and NOR
JK flip flop using NAND and NOR
Public
Logic Gates
Logic Gates
Public
1 bit magnitude comparator
1 bit magnitude comparator
Public
Serial In Serial Out Shift Register - D flip flop
Serial In Serial Out Shift Register - D flip flop
Public
half adder using nand gates
half adder using nand gates
Public
Flip-Flops using NAND Gate
Flip-Flops using NAND Gate
Public
Half adder and full adder
Half adder and full adder
Public
SERIAL IN PARALLEL OUT SHIFT REGISTER
SERIAL IN PARALLEL OUT SHIFT REGISTER
Public
8:1 Mux using Logic Gates
8:1 Mux using Logic Gates
Public
Flip-Flops
Flip-Flops
Public
Ring and Johnson Counter
Ring and Johnson Counter
Public
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