BINARY TO GRAY(EXP-4)

GRAY TO BINARY(EXP-5)

EXP 6(BCD to EXCESS 3)

Half subtractor(EXP-10)

FULL ADDER(EXP-8B)

HALF ADDER(EXP-8A)

1:4DEMUX(EXP-15B)

SISO

AND USING NOR

OR USING NAND

OR USING NOR

NOT USING NOR

AND USING NAND(EXP-1A)

NOT USING NAND

XOR USING NAND

XOR using NOR

exp 2

exp 3

4-Bit Synchronous Up Counter

PARITY CHECKER exp 13 b

Experiment 9

exp 11 full subtractor

4:1 MUX exp 15 a

jk flip flop nand gate(EXP 23)

D flip flop nand gate(EXP 22)

octal to binary (EXP 20)

SR flip flop nand gate (EXP 21)

t flip flop nand gate(EXP 24)

EXP 12 FULL SUBTRACTOR USING TWO HALF SUBTRACTOR

Untitled

4 bit Synchronous DOWN Counter

PAIRITY CHECKING

FULL SUBTRACTOR USING 4:1 MUX_EXP 17

EXP 7(EXCESS-3 TO BCD)

2-BIT COMPARATOR exp 14

Untitled

XOR USING NAND

SIPO

4:2 PRIORITY ENCODER(EXP-18)

even parity generator exp 13 a

EXP 1 B

(Exp 17)Implementation of Full Subtractor using MUX IC 4539B (4:1 MUX).

exp 19 Realization of the internal architecture of 3:8 Decoder using basic gates

Full Subtractor using 4:1 MUX

(Exp 16) Implementation of Full Adder using MUX IC 4539B (4:1 MUX)