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Shivam Jha

Member since: 3 years

Educational Institution: University of Engineering & Management

Country: India

SUBTRACTOR CIRCUIT

SUBTRACTOR CIRCUIT
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Experiment 5 : Gray Code to Binary

Experiment 5 : Gray Code to Binary
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BCD to decimal

BCD to decimal
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Bidirectional Shift Register

Bidirectional Shift Register
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2 bit magnitude Comparator

2 bit magnitude Comparator
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BCD to Excess-3 code

BCD to Excess-3 code
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Half Subtractor Circuit

Half Subtractor Circuit
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Implementation of Half Adder

Implementation of Half Adder
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Implementation of Full Adder

Implementation of Full Adder
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FULL ADDER WITH BASIC GATES

FULL ADDER WITH BASIC GATES
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Half Subtractor

Half Subtractor
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Full Subtractor using Half Subtractors

Full Subtractor using Half Subtractors
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EXPERIMENT 10 11 12

EXPERIMENT 10 11 12
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EX 1B Q3

EX 1B Q3
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XOR with NAND

XOR with NAND
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XOR with NOR

XOR with NOR
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Determination of Prime or non prime

Determination of Prime or non prime
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EX 1B Q2

EX 1B Q2
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OR using NAND

OR using NAND
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AND USING NOR

AND USING NOR
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EX 1B Q1

EX 1B Q1
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NOT Using NOR

NOT Using NOR
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AND USING NAND

AND USING NAND
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OR USING NOR

OR USING NOR
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Gray Code from Binary Code

Gray Code from Binary Code
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Excess -3 code to BCD.

Excess -3 code to BCD.
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EVEN PARITY CHECKER

EVEN PARITY CHECKER
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4:2 PRIORITY ENCODER

4:2 PRIORITY ENCODER
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4:2 p encoder

4:2 p encoder
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exp 19

exp 19
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EXP:14

EXP:14
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EXP:15(B)

EXP:15(B)
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BCD to decimal

BCD to decimal
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BCD to Decimal - 9th

BCD to Decimal - 9th
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T Flip Flop

T Flip Flop
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Flip-Flops using NAND Gate

Flip-Flops using NAND Gate
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2 bit magnitude Comparator

2 bit magnitude Comparator
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Implementation of FULL Adder by using 2 half Adders and an OR gate

Implementation of FULL Adder by using 2 half Adders and an OR gate
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EXP 2 ODD AND EVEN NUMBER

EXP 2 ODD AND EVEN NUMBER
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Half adder using basic gates

Half adder using basic gates
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Even Parity Generator

Even Parity Generator
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FULL SUBTRACTOR CIRCUIT

FULL SUBTRACTOR CIRCUIT
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EXP: 15(A)

EXP: 15(A)
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Bidirectional Shift Register

Bidirectional Shift Register
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