SUBTRACTOR CIRCUIT

Experiment 5 : Gray Code to Binary

BCD to decimal

Bidirectional Shift Register

2 bit magnitude Comparator

BCD to Excess-3 code

Half Subtractor Circuit

Implementation of Half Adder

Implementation of Full Adder

FULL ADDER WITH BASIC GATES

Half Subtractor

Full Subtractor using Half Subtractors

EXPERIMENT 10 11 12

EX 1B Q3

XOR with NAND

XOR with NOR

Determination of Prime or non prime

EX 1B Q2

OR using NAND

AND USING NOR

EX 1B Q1

NOT Using NOR

AND USING NAND

OR USING NOR

Gray Code from Binary Code

Excess -3 code to BCD.

EVEN PARITY CHECKER

4:2 PRIORITY ENCODER

4:2 p encoder

exp 19

EXP:14

EXP: 15(A)

EXP:15(B)

BCD to decimal

BCD to Decimal - 9th

T Flip Flop

Flip-Flops using NAND Gate

2 bit magnitude Comparator

Bidirectional Shift Register

Implementation of FULL Adder by using 2 half Adders and an OR gate

EXP 2 ODD AND EVEN NUMBER

Half adder using basic gates

Even Parity Generator

FULL SUBTRACTOR CIRCUIT