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H_2_Gauri Sharma

Member since: 3 years

Educational Institution: Gla University, Mathura

Country: India

NOT Gate implementation

NOT Gate implementation
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to verify the truth table of AND Gate

to verify the truth table of AND Gate
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verify the truth table of OR Gate

verify the truth table of OR Gate
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design full adder/subtractor

design full adder/subtractor
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serial in serial out

serial in serial out
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mod 4 counter

mod 4 counter
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4 bit adder

4 bit adder
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ALU operation

ALU operation
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SR & JK flip flops

SR & JK flip flops
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HALF ADDER

HALF ADDER
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Half Subractor

Half Subractor
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Seven segement display

Seven segement display
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Seven segement display

Seven segement display
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