project.name

Ishu Gautam

Member since: 3 years

Educational Institution: Not Entered

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4 BIT BINARY ADDER

4 BIT BINARY ADDER
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Half Adder

Half Adder
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Half Adder

Half Adder
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SR Flip Flop

SR Flip Flop
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SR Flip Flop

SR Flip Flop
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Syncronoush MOD-4 Counter

Syncronoush MOD-4 Counter
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Syncronoush MOD-4 Counter

Syncronoush MOD-4 Counter
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Half Adder

Half Adder
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Full Adder

Full Adder
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4 Bit Binary Adder /Subtractor

4 Bit Binary Adder /Subtractor
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SR Flip Flop Using NAND Gate

SR Flip Flop Using NAND Gate
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D Flip Flop

D Flip Flop
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JK Flipo Flop Using NAND Gate

JK Flipo Flop Using NAND Gate
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T Flip FLOP

T Flip FLOP
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Experiment 2 - Implementation of Basic Gates (NOT, AND, OR, XOR) using NAND Gate

Experiment 2 - Implementation of Basic Gates (NOT, AND, OR, XOR) using NAND Gate
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