project.name

H_01_Gaurav Yadav

Member since: 3 years

Educational Institution: Not Entered

Country: India

7'th segment display

7'th segment display
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SR & JK filp flops

SR & JK filp flops
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ALU operations

ALU operations
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4 bit adder

4 bit adder
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serial in serial out

serial in serial out
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mod 4 counter

mod 4 counter
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Design the full adder/subtractor

Design the full adder/subtractor
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to verigy the truth table of AND Gate

to verigy the truth table of AND Gate
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to verify the truth table of OR gate

to verify the truth table of OR gate
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NOT GATE implementation

NOT GATE implementation
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to construct the half adder / subtractor

to construct the half adder / subtractor
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